Canvas Category OEM : Semiconductor
We are the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality.
Schneider Electric Partners with Intel and Applied Materials to Help Decarbonize the Semiconductor Value Chain with New Catalyze Program
Schneider Electric, the leader in the digital transformation of energy management and automation, today launched Catalyze, a new partnership program aimed at accelerating access to renewable energy across the global semiconductor value chain.
Unveiled during SEMICON West 2023, Catalyze is a first-of-its kind program of collaboration among key semiconductor and technology industry leaders to address the supply chain emissions within their industry. The program joins other Schneider Electric supply chain partnership initiatives that seek to leverage the power of supply chain cohorts, including the Energize program for the pharmaceutical industry, and Walmart’s Gigaton PPA program.
A Deeper Look into the New Vistara™ Platform
This is not your run-of-the-mill equipment launch. Vistara is Applied’s most significant new platform in more than a decade – a purpose-built system that has been expertly designed over the past four years by hundreds of engineers from across Applied’s hardware, software, process technology and ecoefficiency teams.
The new Vistara platform is architected based on three pillars: flexibility, intelligence and sustainability. The following animation video highlights the capabilities and components behind each of these pillars.
Pattern-Shaping System Speeds Up Chip Production
Applied Materials has introduced its new Centura Sculpta pattern-shaping system that promises to provide a cost-effective alternative to extreme ultraviolet (EUV) lithography double patterning used to print dense interconnect lines and vias. As a result, the solution can reduce the number of EUV steps, production complexity and costs while potentially improving yields.
To keep advancing transistor performance, power consumption and density, chipmakers must adopt more sophisticated process technologies with tighter critical dimensions. Usage of dual EUV exposure is inevitable to print smaller features with 3-nm, 2-nm and thinner nodes. But double EUV patterning is expensive, lengthy and resource-consuming.
Bringing Next-Generation eBeam Technology Out of the Lab and into the Fab
Challenges to Interconnect Scaling at 3nm and Beyond
Interconnects consist of two key metal components: the metal lines that transfer current within the same device layer and the metal vias that transfer current between layers. Pitch reduction narrows the width of both and increases resistance along with the time needed to move signals across distances. It also increases the voltage drop across a circuit, throttling circuit speed and increasing power dissipation.
While transistor performance improves with scaling, the same cannot be said for interconnect metals. In fact, as dimensions shrink, interconnect via resistance can increase by a factor of 10 (see Figure 1). This results in resistive-capacitive (RC) delays that reduce performance. It also increases power consumption. Interconnects consume close to one third of device power and account for more than 75 percent of RC delay, so improving interconnect resistance is the best way to improve overall device performance.
To enable logic scaling to continue, the industry is developing a new architecture called buried power rail with backside power delivery network (see Figure 4). This architecture routes power to the transistor cell from the back side of the silicon wafer, beneath the transistors. The approach is expected to provide three important benefits: improving voltage losses by as much as 7X; allowing the transistor cell area to be scaled by 20-33 percent; and leaving more cell space for the signal lines which also incur resistance from scaling.