Sequoia Capital

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JITX Launches General Availability And Announces $12M Series A From Sequoia Capital

Date:

Topics: Funding Event, Generative Design

Organizations: JITX, Sequoia Capital

Today we’re announcing the general availability of JITX and that we raised a $12M Series A round, led by Sequoia Capital, with participation from Y Combinator, Funders Club and Liquid 2.

Hardware engineers need a credible way out of the trap they find themselves in. JITX helps by letting them write code that automates their engineering process. To get ahead they can’t just do one design after another – they need reusable code that designs hardware for them. To illustrate this point: a software engineer can upload code to GitHub and thousands of people can reuse that code in their own projects. Using a traditional hardware design flow, each one of those thousands of engineers would have to re-design and re-analyze the same circuit to make sure the design will behave correctly in their product. JITX brings the productivity of software to hardware.

At the same time we were working with enterprise design teams like Northrop Grumman. It turns out that they also needed JITX to address some specific problems. Like everyone else, their biggest challenge is finding and retaining skilled engineers. There just aren’t enough experts to go around, and even entry level positions are getting harder to fill (turns out new EE graduates are more interested in AI than drafting circuit boards). So they use JITX as a way to make their existing experts more productive. They find a lot of value out of checking designs automatically – a manual derating analysis on a complex FPGA board can take months but JITX automates the whole procedure. They are also excited about using code as a more efficient way to coordinate across different teams in the organization. At the end of our iteration process we were quickly designing boards that were at the limit of what traditional factories could build (our thanks to Gerry Partida for an 8/4 stacked microvia with sub 70um trace and space!). For example we built this silicon validation board that included 2500 pins in a complex 300um grid.

Read more at JITX Blog