Chip Design

Assembly Line

Silicon Volley: Designers Tap Generative AI for a Chip Assist

๐Ÿ“… Date:

โœ๏ธ Author: Rick Merritt

๐Ÿ”– Topics: Generative AI, Large Language Model, Computer-aided Design, Chip Design, Virtual Assistant

๐Ÿญ Vertical: Semiconductor

๐Ÿข Organizations: NVIDIA

The work demonstrates how companies in highly specialized fields can train large language models (LLMs) on their internal data to build assistants that increase productivity.

The paper details how NVIDIA engineers created for their internal use a custom LLM, called ChipNeMo, trained on the companyโ€™s internal data to generate and optimize software and assist human designers. Long term, engineers hope to apply generative AI to each stage of chip design, potentially reaping significant gains in overall productivity, said Ren, whose career spans more than 20 years in EDA. After surveying NVIDIA engineers for possible use cases, the research team chose three to start: a chatbot, a code generator and an analysis tool.

On chip-design tasks, custom ChipNeMo models with as few as 13 billion parameters match or exceed performance of even much larger general-purpose LLMs like LLaMA2 with 70 billion parameters. In some use cases, ChipNeMo models were dramatically better.

Read more at NVIDIA Blog