Cadence Design Systems (Cadence)
Canvas Category Software : Engineering : Semiconductor
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and health.
Assembly Line
Cadence Acquires Invecas to Accelerate System Realization
Cadence Design Systems, Inc. (Nasdaq: CDNS) announced that it has acquired Invecas, Inc., a leading provider of design engineering, embedded software and system-level solutions, headquartered in Santa Clara, California. The purchase adds a skilled system design engineering team to Cadence, with expertise in providing customers with custom solutions across chip design, product engineering, advanced packaging and embedded software.
Accelerating trends such as digital transformation of multiple vertical markets and more system companies building custom silicon continue to drive strong design activity. Additionally, with classic Moore’s law slowing down, new “More than Moore” technologies, such as advanced 2.5D/3D packaging and chiplets, are paving the way for significant performance and manufacturing efficiencies. These strategic generational trends, underpinned by advancements in AI, are ushering in a new era of design and spurring a rapidly growing customer need for skilled end-to-end engineering expertise in enabling their custom silicon and system development efforts.
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Autodesk & Cadence: Partnering to Unlock Smarter Product Design and Fuel Innovation
Traditionally, printed circuit board (PCB) designers using Cadence Design Systems tools operated in a silo, isolated from the mechanical design team working with tools like Autodesk Fusion. Teams would play a game of digital ping-pong, tossing files over the virtual wall, hoping everything gets noticed in the right place, at the right time, and by the right people.
This week at Autodesk University, we were excited to announce our new partnership with Cadence Design Systems, the leader in electronic systems design tools, which aims to bridge this gap between electronic and mechanical design teams. The integration connects specialized Cadence PCB technologies directly with Autodesk Fusion, advancing its powerful CAD, CAM, and PCB design capabilities to streamline ECAD to MCAD workflows and transform smart product design.
Together, the partnership brings cloud-based integration between Fusion and Cadence Allegro X and OrCAD X. The integrated solution is another example of Autodesk’s commitment to an open ecosystem and to improve collaboration across electronics and mechanical design teams.
Cadence Design Is Working With Renesas To Build The World’s First LLM Tool For Up-Front Chip Design
Cadence has been aggressively rolling out reinforcement learning-based tools to help chip design teams accelerate the processes of digital design, debugging, verification, PCB layout, and multi-physics optimization. Customers have been eating it up, especially the physical design optimizer “Cerebrus” and the underlying cross-platform consolidated database, “JedAI.”
Now, the company has focused on the most challenging part of designing a chip: defining the specs and creating the first clean version of the design that drives the rest of the entire workflow. Renesas and Cadence have collaborated to develop a novel approach to address the up-front design work by leveraging LLMs, significantly reducing the time and effort from specification to final design. The chip design verification, debugging, and implementation phases remain the same today. They call this accelerating “Correct by Construction” design methodology.
Using an LLM, the team can demonstrate interrogating the plan for compliance with specifications and other design and project documents, in areas such as IP connections for data, control, and test, and other requirements specified in the IP and chip level specifications. These steps of cleaning the design code can take individual engineers and the team weeks of design time and hundreds of meetings to reduce the number of bugs they encounter during the simulation and implementation stages of the project. By using an LLM, Cadence hopes to significantly streamline this process.
🧠 AI PCB Design: How Generative AI Takes Us From Constraints To Possibilities
Cadence customers are already reaping the benefits of generative AI within our Joint Enterprise Data and AI (JedAI) Platform. Chip designers are realizing Cadence Cerebrus AI to design chips that are faster, cheaper, and more energy efficient. Now, we’re bringing this generative AI approach to an area of EDA that has traditionally been highly manual—PCB placement and routing.
Allegro X AI flips the PCB design process on its head. Rather than present the operator with a blank canvas, it will take a list of components and constraints that need to be satisfied in the end result and sift through a plethora of design possibilities, encompassing varied placement and routing options. This is hugely powerful for hardware engineers focused on design space exploration (DSE). This has long been par for the course in IC design yet it has more recently become critical to PCB due to the fact that today’s IC complexity doesn’t reduce when it gets onto the PCB—it increases.
However, it’s important to understand that this isn’t Cadence replacing traditional compute algorithms and automation approaches with AI. We remain as committed to accuracy and “correct by construction” as we’ve ever been, and while Allegro X AI is trained on extensive real-world datasets of successful and failed designs, we don’t use that data to determine correctness.
Cadence Strengthens Tensilica Vision and AI Software Partner Ecosystem for Advanced Automotive, Mobile, Consumer and IoT Applications
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has welcomed Kudan and Visionary.ai to the Tensilica software partner ecosystem, bringing industry-leading simultaneous localization and mapping (SLAM) and AI image signal processor (ISP) solutions to Cadence® Tensilica® Vision DSPs and AI platforms. The broad Tensilica Vision and AI software ecosystem includes more than 50 partners developing solutions for these platforms, covering automotive, smartphone apps, IoT, software services, and many other segments.
Kudan is an industry leader in visual odometry and an early implementer of SLAM algorithms. Visionary.ai’s efficient AI-ISP enables customers to implement a camera pipeline with resolutions greater than full HD while operating at over 30fps on the Tensilica NNA110 accelerator.
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Designing Billions of Circuits with Code
Bringing EDA to silicon helped solve daunting challenges in chip making. A chip is built in layers. Now you have to wire connections in 3-D, taking into consideration layer-to-layer connections called vias.
AI-Powered Verification
“We see AI as a disruptive technology that will in the long run eliminate, and in the near term reduce the need for verification,” says Anupam Bakshi, CEO and founder of Agnisys. “We have had some early successes in using machine learning to read user specifications in natural language and directly convert them into SystemVerilog Assertions (SVA), UVM testbench code, and C/C++ embedded code for test and verification.”
There is nothing worse than spending time and resources to not get the desired result, or for it to take longer than necessary. “In formal, we have multiple engines, different algorithms that are working on solving any given property at any given time,” says Pete Hardee, director for product management at Cadence. “In effect, there is an engine race going on. We track that race and see for each property which engine is working. We use reinforcement learning to set the engine parameters in terms of which engines I’m going to use and how long to run those to get better convergence on the properties that didn’t converge the first time I ran it.”
Autonomous Design Automation: How Far Are We?
As an industry, we will refine the different levels of Autonomous Design Automation further over the years to come. Eventually, the combination of the different steps of the flow with AI/ML will unlock even further productivity improvements. How long will it be until designers define a function in a higher-level language like SysML and, based on the designer’s requirements, autonomously implement it as a hardware/software system after AI/ML-controlled design-space exploration?
Improving PPA In Complex Designs With AI
The goal of chip design always has been to optimize power, performance, and area (PPA), but results can vary greatly even with the best tools and highly experienced engineering teams. AI works best in design when the problem is clearly defined in a way that AI can understand. So an IC designer must first see if there is a problem that can be tied to a system’s ability to adapt to, learn, and generalize knowledge/rules, and then apply these knowledge/rules to an unfamiliar scenario.
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How To Measure ML Model Accuracy
Machine learning (ML) is about making predictions about new data based on old data. The quality of any machine-learning algorithm is ultimately determined by the quality of those predictions.
However, there is no one universal way to measure that quality across all ML applications, and that has broad implications for the value and usefulness of machine learning.
Edge-Inference Architectures Proliferate
What makes one AI system better than another depends on a lot of different factors, including some that aren’t entirely clear.
The new offerings exhibit a wide range of structure, technology, and optimization goals. All must be gentle on power, but some target wired devices while others target battery-powered devices, giving different power/performance targets. While no single architecture is expected to solve every problem, the industry is in a phase of proliferation, not consolidation. It will be a while before the dust settles on the preferred architectures.