Canon aims to ship low-cost ‘stamp’ machine this year to disrupt chipmaking
First unveiled in mid-October, Canon’s nanoimprint lithography — a technology under development for more than 15 years but which the company says is only now commercially viable — stamps chip designs on to silicon wafers rather than etching them using light. The process, says Canon, will be “one digit” cheaper and use up to 90 per cent less power than Netherlands-based ASML’s market-dominating and light-based extreme ultraviolet (EUV) technology.
How an ASML Lithography Machine Moves a Wafer
Closing the design-to-manufacturing gap for optical devices
We introduce neural lithography to address the ‘design-to-manufacturing’ gap in computational optics. Computational optics with large design degrees of freedom enable advanced functionalities and performance beyond traditional optics. However, the existing design approaches often overlook the numerical modeling of the manufacturing process, which can result in significant performance deviation between the design and the fabricated optics. To bridge this gap, we, for the first time, propose a fully differentiable design framework that integrates a pre-trained photolithography simulator into the model-based optical design loop. Leveraging a blend of physics-informed modeling and data-driven training using experimentally collected datasets, our photolithography simulator serves as a regularizer on fabrication feasibility during design, compensating for structure discrepancies introduced in the lithography process. We demonstrate the effectiveness of our approach through two typical tasks in computational optics, where we design and fabricate a holographic optical element (HOE) and a multi-level diffractive lens (MDL) using a two-photon lithography system, showcasing improved optical performance on the task-specific metrics.
Breakthrough Digital Lithography Technology From Applied Materials and Ushio to Enable More Powerful Computing Systems for the AI Era
Applied Materials, Inc. and Ushio, Inc. announced a strategic partnership to accelerate the industry’s roadmap for heterogeneous integration (HI) of chiplets into 3D packages. The companies are jointly bringing to market the first digital lithography system specifically designed for patterning the advanced substrates needed in the Artificial Intelligence (AI) era of computing.
The new DLT system is the only lithography technology that can achieve the resolution necessary for advanced substrate applications while delivering throughput levels required for high-volume production. With the ability to pattern less than 2-micron line widths, the system enables the highest area density for chiplet architectures on any substrate, including wafers or large panels made of glass or organic materials. The DLT system is uniquely designed to solve unpredictable substrate warpage issues and achieve overlay accuracy. Production systems have already been shipped to multiple customers, and 2-micron patterning has been demonstrated on glass and other advanced package substrates.
Nanoimprint lithography semiconductor manufacturing system that covers diverse applications with simple patterning mechanism
On October 13, 2023, Canon announced today the launch of the FPA-1200NZ2C nanoimprint semiconductor manufacturing equipment, which executes circuit pattern transfer, the most important semiconductor manufacturing process. By bringing to market semiconductor manufacturing equipment with nanoimprint lithography (NIL) technology, in addition to existing photolithography systems, Canon is expanding its lineup of semiconductor manufacturing equipment to meet the needs of a wide range of users by covering from the most advanced semiconductor devices to the existing devices.
Canon’s NIL technology enables patterning with a minimum linewidth of 14 nm2, equivalent to the 5-nm-node3 required to produce most advanced logic semiconductors which are currently available. Furthermore, with further improvement of mask technology, NIL is expected to enable circuit patterning with a minimum linewidth of 10 nm, which corresponds to 2-nm-node.
High-NA EUV Progress And Problems
How immersion lithography saved Moore’s Law
In December 2001, ASML researcher Jan Mulkens (now an ASML Fellow) attended an industry conference on 157-nanometer lithography in the United States where industry professionals came together to identify potential next steps. Their discussion honed in on adding a layer of purified water under the lens to sharpen the resolution, an optical phenomenon first discovered and harnessed by microscope pioneers Robert Hooke and Antoni van Leeuwenhoek, and first described for use in lithography by IBM in the 1980s. Jan and his colleagues realized that this optical technique could extend 193-nanometer lithography further, bypassing the industry’s burning challenge of trying to fix 157-nanometer lithography. Furthermore, by using water as the optical fluid, all of the existing optics, masks and photoresists could continue to be used. This was the best chance to keep Moore’s Law going.
“Projecting light through highly purified water would allow significantly smaller chip features to be printed, because the liquid allows the design of an optical lens that more accurately images the fine patterns on the wafer,” explains Jan. “But when we first started thinking about using this principle in a lithography machine, people found it odd. Water was associated with splashes, droplets and bubbles – would that really work in a complex and highly accurate imaging system?” Introducing water into the system that might not flow safely and securely through a hose appeared to be an impossible task.
TWINSCAN: 20 years of lithography innovation
“It was limited new technology, but what was a revolution about the TWINSCAN was the swapping of the stages,” says Bert. “Lots of things were normal developments, but that chuck swap was different. We just had to make it work.”
And thus, the TWINSCAN platform was born. TWINSCAN was the first – and is still the only – lithography system platform with two complete wafer table modules (or wafer stages). Wafers are loaded onto the wafer table modules alternately. When the wafer on table one is being exposed, another wafer is loaded on table two and then aligned and mapped. The tables then swap position so that the wafer on table two is exposed while the wafer on table one is unloaded. A new wafer is then loaded, aligned and mapped.
IBM Unveils World's First 2 Nanometer Chip Technology, Opening a New Frontier for Semiconductors
IBM (NYSE: IBM) today unveiled a breakthrough in semiconductor design and process with the development of the world’s first chip announced with 2 nanometer (nm) nanosheet technology. Semiconductors play critical roles in everything from computing, to appliances, to communication devices, transportation systems, and critical infrastructure.
The potential benefits of these advanced 2 nm chips could include:
- Quadrupling cell phone battery life, only requiring users to charge their devices every four days.
- Slashing the carbon footprint of data centers, which account for one percent of global energy use. Changing all of their servers to 2 nm-based processors could potentially reduce that number significantly.
- Drastically speeding up a laptop’s functions, ranging from quicker processing in applications, to assisting in language translation more easily, to faster internet access.
- Contributing to faster object detection and reaction time in autonomous vehicles like self-driving cars.