Synopsys

Software : Engineering : Digital Twin : Computer and Electronic

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Mountain View, California, United States

NASDAQ: SNPS

Synopsys technology is at the heart of innovations that are changing the way people work and play. Self-driving cars. Machines that learn. Lightning-fast communication across billions of devices in the datasphere. These breakthroughs are ushering in the era of Smart Everything―where devices are getting smarter and connected, and security is an important consideration. Powering this new era of digital innovation are high-performance silicon chips and exponentially growing amounts of software content. Synopsys is at the forefront of Smart Everything with the world’s most advanced technologies for chip design, verification, IP integration, and software security and quality testing. We help our customers innovate from silicon to software so they can bring Smart Everything to life.

Assembly Line

Making The Most Of Data Lakes

Date:

Author: Anne Meixner

Topics: MLOps

Vertical: Semiconductor

Organizations: PDF Solutions, Synopsys

Data management and data analysis necessitates understanding the data storage and data compute options to design an optimal solution. This is made more difficult by the sheer volume of data generated by the design and manufacturing of semiconductor devices. There are more sensors being added into equipment, more complex heterogeneous chip architectures, and increased demands for reliability — which in turn increase the amount of simulation, inspection, metrology, and test data being generated.

Connecting different data sources is extremely valuable. It allows feed-forward decisions on manufacturing processes (package type, skipping burn-in), and feedback in order to trace causes of excursions (yield, quality, and customer returns).

“An understanding of the semiconductor manufacturing process and relationships throughout are essential for some applications,” said Jeff David, vice president of AI solutions at PDF Solutions. “For example, how can I use wafer equipment history and tool sensor data to predict the failure propensity of a chip at final test? How does time delay between process and test steps determine what data is useful in finding a root cause of a failure mode? What failure modes are predictable with which datasets? How do preceding process steps affect the data collected at a given process step?”

Read more at Semiconductor Engineering

Industrial CT Scanning: Automated Defect Detection for Turbine Blades | Synopsys

Improving Yield With Machine Learning

Date:

Author: Laura Peters

Topics: Machine Learning, Convolutional Neural Network, ResNet

Vertical: Semiconductor

Organizations: KLA, Synopsys, CyberOptics, Macronix

Machine learning is becoming increasingly valuable in semiconductor manufacturing, where it is being used to improve yield and throughput.

Synopsys engineers recently found that a decision tree deep learning method can classify 98% of defects and features at 60X faster retraining time than traditional CNNs. The decision tree utilizes 8 CNNs and ResNet to automatically classify 12 defect types with images from SEM and optical tools.

Macronix engineers showed how machine learning can expedite new etch process development in 3D NAND devices. Two parameters are particularly important in optimizing the deep trench slit etch — bottom CD and depth of polysilicon etch recess, also known as the etch stop.

KLA engineers, led by Cheng Hung Wu, optimized the use of a high landing energy e-beam inspection tool to capture defects buried as deep as 6µm in a 96-layer ONON stacked structure following deep trench etch. The e-beam tool can detect defects that optical inspectors cannot, but only if operated with high landing energy to penetrate deep structures. With this process, KLA was looking to develop an automated detection and classification system for deep trench defects.

Read more at Semiconductor Engineering

Designing Billions of Circuits with Code

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Topics: Electronic Design Automation

Vertical: Semiconductor

Organizations: Cadence, Synopsys

Bringing EDA to silicon helped solve daunting challenges in chip making. A chip is built in layers. Now you have to wire connections in 3-D, taking into consideration layer-to-layer connections called vias.

Read more at Asianometry

Improving PPA In Complex Designs With AI

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Author: John Koon

Topics: Reinforcement Learning, Generative Design

Vertical: Semiconductor

Organizations: Google, Cadence, Synopsys

The goal of chip design always has been to optimize power, performance, and area (PPA), but results can vary greatly even with the best tools and highly experienced engineering teams. AI works best in design when the problem is clearly defined in a way that AI can understand. So an IC designer must first see if there is a problem that can be tied to a system’s ability to adapt to, learn, and generalize knowledge/rules, and then apply these knowledge/rules to an unfamiliar scenario.

Read more at Semiconductor Engineering

Fabs Drive Deeper Into Machine Learning

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Author: Anne Meixner

Topics: machine learning, machine vision, defect detection, convolutional neural network

Vertical: Semiconductor

Organizations: GlobalFoundries, KLA, SkyWater Technology, Onto Innovation, CyberOptics, Hitachi, Synopsys

For the past couple decades, semiconductor manufacturers have relied on computer vision, which is one of the earliest applications of machine learning in semiconductor manufacturing. Referred to as Automated Optical Inspection (AOI), these systems use signal processing algorithms to identify macro and micro physical deformations.

Defect detection provides a feedback loop for fab processing steps. Wafer test results produce bin maps (good or bad die), which also can be analyzed as images. Their data granularity is significantly larger than the pixelated data from an optical inspection tool. Yet test results from wafer maps can match the splatters generated during lithography and scratches produced from handling that AOI systems can miss. Thus, wafer test maps give useful feedback to the fab.

Read more at Semiconductor Engineering

How To Measure ML Model Accuracy

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Author: Bryon Moyer

Topics: machine learning

Organizations: Ansys, Brainome, Cadence, Flex Logix, Synopsys, Xilinx

Machine learning (ML) is about making predictions about new data based on old data. The quality of any machine-learning algorithm is ultimately determined by the quality of those predictions.

However, there is no one universal way to measure that quality across all ML applications, and that has broad implications for the value and usefulness of machine learning.

Read more at Semiconductor Engineering

Edge-Inference Architectures Proliferate

Date:

Author: Bryon Moyer

Topics: AI, machine learning, edge computing

Vertical: Semiconductor

Organizations: Cadence, Hailo, Google, Flex Logix, BrainChip, Synopsys, GrAI Matter, Deep Vision, Maxim Integrated

What makes one AI system better than another depends on a lot of different factors, including some that aren’t entirely clear.

The new offerings exhibit a wide range of structure, technology, and optimization goals. All must be gentle on power, but some target wired devices while others target battery-powered devices, giving different power/performance targets. While no single architecture is expected to solve every problem, the industry is in a phase of proliferation, not consolidation. It will be a while before the dust settles on the preferred architectures.

Read more at Semiconductor Engineering