Canvas Category Software : Engineering : Semiconductor
Synopsys technology is at the heart of innovations that are changing the way people work and play. Self-driving cars. Machines that learn. Lightning-fast communication across billions of devices in the datasphere. These breakthroughs are ushering in the era of Smart Everything―where devices are getting smarter and connected, and security is an important consideration. Powering this new era of digital innovation are high-performance silicon chips and exponentially growing amounts of software content. Synopsys is at the forefront of Smart Everything with the world’s most advanced technologies for chip design, verification, IP integration, and software security and quality testing. We help our customers innovate from silicon to software so they can bring Smart Everything to life.
Synopsys to buy engineering software firm Ansys in $35 billion deal
Chip design software maker Synopsys, opens new tab said it would buy Ansys, opens new tab in a $35 billion cash-and-stock deal. The transaction will create a massive new player in a sector of the business software industry that is already highly consolidated, which Wells Fargo said in a note creates regulatory uncertainty. After the news, Synopsys shares were up 3.8% to $513, but Ansys shares were down 4.8% to $329.86.
Introducing the Synopsys EDA Data Analytics Solution
Challenges In Ramping New Manufacturing Processes
Intel and Synopsys Expand Partnership to Enable Leading IP on Intel Advanced Process Nodes
Intel (Nasdaq: INTC) and Synopsys (Nasdaq: SNPS) announced that they have entered into a definitive agreement to expand the companies’ long-standing IP (intellectual property) and EDA (electronic design automation) strategic partnership with the development of a portfolio of IP on Intel 3 and Intel 18A for Intel’s foundry customers. The availability of key IP on Intel advanced process nodes will create a more robust offering for new and existing Intel Foundry Services (IFS) customers.
As part of the transaction, Synopsys will enable a range of its standardized interface IP portfolio on Intel’s leading-edge process technologies. As a result, Intel’s foundry customers will gain access to industry-leading IPs built on Intel advanced process technologies and be able to accelerate design execution and project schedules for system-on-chips (SoCs).
The Impact Of Machine Learning On Chip Design
⭐ Hunting For Hardware-Related Errors In Data Centers
The data center computational errors that Google and Meta engineers reported in 2021 have raised concerns regarding an unexpected cause — manufacturing defect levels on the order of 1,000 DPPM. Specific to a single core in a multi-core SoC, these hardware defects are difficult to isolate during data center operations and manufacturing test processes. In fact, SDEs can go undetected for months because the precise inputs and local environmental conditions (temperature, noise, voltage, clock frequency) have not yet been applied.
For instance, Google engineers noted ‘an innocuous change to a low-level library’ started to give wrong answers for a massive-scale data analysis pipeline. They went on to write, “Deeper investigation revealed that these instructions malfunctioned due to manufacturing defects, in a way that could only be detected by checking the results of these instructions against the expected results; these are ‘silent’ corrupt execution errors, or CEEs.”
Engineers at Google further confirmed their need for internal data, “Our understanding of CEE impacts is primarily empirical. We have observations of the form, ‘This code has miscomputed (or crashed) on that core.’ We can control what code runs on what cores, and we partially control operating conditions (frequency, voltage, temperature). From this, we can identify some mercurial cores. But because we have limited knowledge of the detailed underlying hardware, and no access to the hardware-supported test structures available to chip makers, we cannot infer much about root causes.”
Designing in the Age of AI
Yield Is Top Issue For MicroLEDs
Early test results indicate yield issues at chip transfer, array-to-driver bonding, and other relatively new processes. High cost for this immature technology is keeping microLED displays from making the prototype-to-production leap. And because probers are not well suited to testing thousands of microLED pixels in densely packed arrays, DFT with self-testing is employed, which enables lifecycle testing — at ATE, post-assembly test, and in the field.
For instance, Dialog Semiconductor, a Renesas Company, developed a testing scheme for a white adaptive headlight module containing a 20,000-microLED array with 40µm pitch. “It’s a very good example of how a DFT circuit is not just overhead and cost to buy quality,” said Hans Martin von Staudt, director of Design-for-Test at Renesas. “Instead, it serves a valuable function over the lifetime of the chip. So we needed a DFT scheme with high-diagnostic coverage of the assembly process for pinpointing process weaknesses while enabling in-field monitoring.”
Inspection and testing methods are improving in their ability to identify and segregate out-of-spec product. Mass transfer methods that remove microLED die from wafers or film carriers and position them on IC drivers (for small AR/VR, watch and headlights) or TFT PCBs (for TVs), must easily separate known good die (KGD) from failures and underperforming die.
Yield targets for most microLED display apps are high (see figure 1) because the human eye can quickly spot missing pixels. To put yield targets in perspective, an 8K TV contains 99 million microLED chips. So if the defectivity rate is 0.5%, 520,000 devices must be removed and replaced. Top Engineering estimates this process would take 144 hours, making it cost-prohibitive until repair cost (removal and replacement of individual microLEDs) can be accelerated.
Modeling Silicon Photonics Process Parameter Variations in Synopsys OptoCompiler-OptSim | Synopsys
Synopsys helps semiconductor designers accelerate chip design and development on Google Cloud
EDA software is a large consumer of high performance computing capacity in the cloud. With the release of Synopsys Cloud bring-your-own-cloud (BYOC) solution on Google Cloud, chip designers can now scale their Google Cloud infrastructure with Synopsys’s leading EDA tools under the flexible FlexEDA pay-per-use model and access unlimited EDA software license availability on-demand by the hour or minute.
Making The Most Of Data Lakes
Data management and data analysis necessitates understanding the data storage and data compute options to design an optimal solution. This is made more difficult by the sheer volume of data generated by the design and manufacturing of semiconductor devices. There are more sensors being added into equipment, more complex heterogeneous chip architectures, and increased demands for reliability — which in turn increase the amount of simulation, inspection, metrology, and test data being generated.
Connecting different data sources is extremely valuable. It allows feed-forward decisions on manufacturing processes (package type, skipping burn-in), and feedback in order to trace causes of excursions (yield, quality, and customer returns).
“An understanding of the semiconductor manufacturing process and relationships throughout are essential for some applications,” said Jeff David, vice president of AI solutions at PDF Solutions. “For example, how can I use wafer equipment history and tool sensor data to predict the failure propensity of a chip at final test? How does time delay between process and test steps determine what data is useful in finding a root cause of a failure mode? What failure modes are predictable with which datasets? How do preceding process steps affect the data collected at a given process step?”
Industrial CT Scanning: Automated Defect Detection for Turbine Blades | Synopsys
Improving Yield With Machine Learning
Machine learning is becoming increasingly valuable in semiconductor manufacturing, where it is being used to improve yield and throughput.
Synopsys engineers recently found that a decision tree deep learning method can classify 98% of defects and features at 60X faster retraining time than traditional CNNs. The decision tree utilizes 8 CNNs and ResNet to automatically classify 12 defect types with images from SEM and optical tools.
Macronix engineers showed how machine learning can expedite new etch process development in 3D NAND devices. Two parameters are particularly important in optimizing the deep trench slit etch — bottom CD and depth of polysilicon etch recess, also known as the etch stop.
KLA engineers, led by Cheng Hung Wu, optimized the use of a high landing energy e-beam inspection tool to capture defects buried as deep as 6µm in a 96-layer ONON stacked structure following deep trench etch. The e-beam tool can detect defects that optical inspectors cannot, but only if operated with high landing energy to penetrate deep structures. With this process, KLA was looking to develop an automated detection and classification system for deep trench defects.
Designing Billions of Circuits with Code
Bringing EDA to silicon helped solve daunting challenges in chip making. A chip is built in layers. Now you have to wire connections in 3-D, taking into consideration layer-to-layer connections called vias.
Improving PPA In Complex Designs With AI
The goal of chip design always has been to optimize power, performance, and area (PPA), but results can vary greatly even with the best tools and highly experienced engineering teams. AI works best in design when the problem is clearly defined in a way that AI can understand. So an IC designer must first see if there is a problem that can be tied to a system’s ability to adapt to, learn, and generalize knowledge/rules, and then apply these knowledge/rules to an unfamiliar scenario.
Fabs Drive Deeper Into Machine Learning
For the past couple decades, semiconductor manufacturers have relied on computer vision, which is one of the earliest applications of machine learning in semiconductor manufacturing. Referred to as Automated Optical Inspection (AOI), these systems use signal processing algorithms to identify macro and micro physical deformations.
Defect detection provides a feedback loop for fab processing steps. Wafer test results produce bin maps (good or bad die), which also can be analyzed as images. Their data granularity is significantly larger than the pixelated data from an optical inspection tool. Yet test results from wafer maps can match the splatters generated during lithography and scratches produced from handling that AOI systems can miss. Thus, wafer test maps give useful feedback to the fab.
How To Measure ML Model Accuracy
Machine learning (ML) is about making predictions about new data based on old data. The quality of any machine-learning algorithm is ultimately determined by the quality of those predictions.
However, there is no one universal way to measure that quality across all ML applications, and that has broad implications for the value and usefulness of machine learning.
Edge-Inference Architectures Proliferate
What makes one AI system better than another depends on a lot of different factors, including some that aren’t entirely clear.
The new offerings exhibit a wide range of structure, technology, and optimization goals. All must be gentle on power, but some target wired devices while others target battery-powered devices, giving different power/performance targets. While no single architecture is expected to solve every problem, the industry is in a phase of proliferation, not consolidation. It will be a while before the dust settles on the preferred architectures.