Semiconductor
This industry comprises establishments primarily engaged in manufacturing semiconductors and other components for electronic applications. Examples of products made by these establishments are capacitors, resistors, microprocessors, bare and loaded printed circuit boards, electron tubes, electronic connectors, and computer modems.
Assembly Line
How ASML took over the chipmaking chessboard
Yet in 2017, after an investment of $6.5 billion in R&D over 17 years, ASML’s bet began to pay off. That year the company shipped 10 of its EUV machines, which cost over $100 million each, and announced that dozens more were on backorder. EUV machines went to the titans of semiconductor manufacturing—Intel, Samsung, and Taiwan Semiconductor Manufacturing Company (TSMC)—and a small number of others. With a brighter light source (meaning less time needed to impart patterns), among other improvements, the machines were capable of faster production speeds. The leap to EUV finally made economic sense to chipmakers, putting ASML essentially in a monopoly position.
The next big idea for ASML, according to van den Brink and other company executives who spoke with MIT Technology Review, is hyper-NA technology. The company’s high-NA machines have a numerical aperture of .55. Hyper-NA tools would have a numerical aperture higher than 0.7. What that ultimately means is that hyper NA, if successful, will allow the company to create machines that let manufacturers shrink transistor dimensions even more—assuming that researchers can devise chip components that work well at such small dimensions. As it was with EUV in the early 2000s, it is still uncertain whether hyper NA is feasible—if nothing else, it could be cost prohibitive. Yet van den Brink projects cautious confidence. It is likely, he says, that the company will ultimately have three offerings available: low NA, high NA, and—if all goes well—hyper NA.
Engineering the Gate-All-Around Transistor
TSMC and Synopsys Bring Breakthrough NVIDIA Computational Lithography Platform to Production
TSMC, the world’s leading foundry, and Synopsys, the leader in silicon to systems design solutions, have integrated NVIDIA cuLitho with their software, manufacturing processes and systems to speed chip fabrication, and in the future support the latest-generation NVIDIA Blackwell architecture GPUs. NVIDIA also introduced new generative AI algorithms that enhance cuLitho, a library for GPU-accelerated computational lithography, dramatically improving the semiconductor manufacturing process over current CPU-based methods.
Computational lithography is the most compute-intensive workload in the semiconductor manufacturing process, consuming tens of billions of hours per year on CPUs. A typical mask set for a chip — a key step in its production — could take 30 million or more hours of CPU compute time, necessitating large data centers within semiconductor foundries. With accelerated computing, 350 NVIDIA H100 systems can now replace 40,000 CPU systems, accelerating production time, while reducing costs, space and power.
TANAKA Establishes Bonding Technology for High-Density Semiconductor Mounting Using AuRoFUSE™ Preforms
TANAKA Kikinzoku Kogyo K.K., which develops industrial precious metals products as one of the core companies of TANAKA Precious Metals, announced that it has established a gold particle bonding technology for high-density mounting of semiconductors using AuRoFUSE™ low-temperature fired paste for gold-to-gold bonding.
AuRoFUSE™ is a composition of submicron-sized gold particles and a solvent that creates a bonding material with low electrical resistance and high thermal conductivity to achieve metal bonding at low temperatures. Using AuRoFUSE™ preforms (dried paste forms), this technology can reach 4 μm fine-pitch mounting with 20 μm bumps. Formed through a thermocompression bonding process (20 MPa at 200°C for 10 seconds), AuRoFUSE™ preforms exhibit compression of approximately 10% in the compressive direction while showing minimal deformation in the horizontal direction. This gives them sufficient bonding strength1 for practical applications, making them suitable for use as gold bumps2. With the main component being gold, which has a high level of chemical stability, AuRoFUSE™ preforms also provide excellent reliability after mounting.
This technology enables miniaturization of semiconductor wiring and greater integration (higher density) for various types of chips. It is expected to contribute to the high-level technical innovation required of advanced technologies, including optical devices such as light-emitting diodes (LEDs) and semiconductor lasers (LDs), and use in digital devices such as personal computers, smartphones, and in-vehicle components.
Accelerate Semiconductor machine learning initiatives with Amazon Bedrock
Manufacturing processes generate large amounts of sensor data that can be used for analytics and machine learning models. However, this data may contain sensitive or proprietary information that cannot be shared openly. Synthetic data allows the distribution of realistic example datasets that preserve the statistical properties and relationships in the real data, without exposing confidential information. This enables more open research and benchmarking on representative data. Additionally, synthetic data can augment real datasets to provide more training examples for machine learning algorithms to generalize better. Data augmentation with synthetic manufacturing data can help improve model accuracy and robustness. Overall, synthetic data enables sharing, enhanced research abilities, and expanded applications of AI in manufacturing while protecting data privacy and security.
Inside Micron Taiwan’s Semiconductor Factory
Canon aims to ship low-cost ‘stamp’ machine this year to disrupt chipmaking
First unveiled in mid-October, Canon’s nanoimprint lithography — a technology under development for more than 15 years but which the company says is only now commercially viable — stamps chip designs on to silicon wafers rather than etching them using light. The process, says Canon, will be “one digit” cheaper and use up to 90 per cent less power than Netherlands-based ASML’s market-dominating and light-based extreme ultraviolet (EUV) technology.
Looking at the future of semiconductor manufacturing
“Moving from 200mm to 300mm wafers increases the size 1.5 x 1.5,” explains Taniguchi. “A simple calculation of the area shows that we have a 2.25 times increase in production. So if you ask how Toshiba is responding to the growing demand for power semiconductors accompanying progress towards carbon neutrality and energy savings, the answer is with increased supply capacity. The introduction of production lines that can handle 300mm wafers became an initiative for everybody in our department. Seeing the entire organization working together heightened my sense of responsibility, as well as excitement from being involved in a new technology. Working out how to set up processes using 300mm manufacturing equipment – it’s a project that exhilarated me.”
Taniguchi knows all about this. “Investing in equipment is front and center in power semiconductor manufacturing, and there is a strong sense of excitement about pioneering technology. You ask yourself if there is a way to increase the productivity of the equipment, to manufacture more power semiconductors, and improve the quality…I’ve spent all day in a clean room fine-tuning the movement of the wafers and devising ways to stabilize the temperature. I got really excited when, after a lot of trial and error, I managed to adjust the conditions to get stable production.
Intel GenAI For Yield
Diffusion networks are much better suited to the task. Real samples with added noise are used to train the model, which learns to denoise them. Crucially, diffusion networks in this application were able to replicate the long tails of the sample data distribution, thus providing accurate predictions of process yield.
In Intel’s research, SPICE parameters, used in the design phase as part of device simulation, are used as input for the deep learning model. Its output is the predicted electrical characteristics of the device as manufactured, or ETEST metrics. And the results show the model is capable of correctly predicting the distribution of ETEST metrics. Circuit yield is defined by the tails of this distribution. So, by correctly predicting the distribution of ETEST metrics, the model is correctly predicting yield.
The potential here is clear: better optimization of chip yields at the design stage means lower costs. Fewer mask respins, shorter development times, and ultimately higher yield would all be strong differentiators for foundries and design teams that can implement models into their PDK/design flows.
Chemicals and materials to play key role in chips as 2-nm milestone nears
James O’Neill, chief technology officer of American chip material maker Entegris, said it is no longer the chipmaking machines, but advanced materials and cleaning solutions that are taking center stage in making advanced production processes possible. “Thirty years ago, it was all about lithography [equipment] to make [transistors on chips] smaller and improve device performance,” O’Neill said. Lithography refers to the key chipmaking process in which integrated circuits are printed onto a chip. How finely a machine can print these circuits generally defines how advanced the chips are.
Kai Beckmann, CEO of Merck’s electronics business, echoed that sentiment. “We are moving from the past two decades where [chipmaking] tools are most important to advance technologies to the next decade, what our customers call the age of materials,” Beckmann said. “The tools are still important, but now materials make all the difference.”
The jump to 2-nm production for logic chips, for example, required a completely new chip architecture. In this new configuration, referred to as gate-all-around (GAA), transistors are stacked in a more complex, three-dimensional way than in earlier, planar configurations. Developing the materials for new transistor configurations like gate-all-around requires innovative materials “that will coat the top, the bottom and the sides equally,” O’Neill said, adding that the industry is engineering ways to do this “at atomic scale dimensions.”
Merck’s Beckmann gave another example of the industry’s material evolution: Copper is widely used as a conductive layer in current chipmaking processes, but to make ever smaller and more advanced chips, the industry is exploring new materials such as molybdenum.
Samsung self-development of'smart sensor' to catch semiconductor yield
Samsung DS develops its own smart sensor system for semiconductor process control and management. A strategy to increase semiconductor yield and productivity, localize existing foreign products. In an attempt to build an intelligent semiconductor production system, it is expected to ultimately implement an artificial fab.
The smart sensor that is currently in development is a sensor that is intended to measure plasma uniformity for wafers, which is precisely to measure and manage this because process performance is as important as being influenced by plasma, such as etching, deposition, and cleaning, which are key to semiconductor processes.
DNP Develops Photomask Process for 3nm EUV Lithography
Dai Nippon Printing Co., Ltd. (DNP) has successfully developed a photomask manufacturing process capable of accommodating the 3-nanometer (10-9 meter) lithography process that supports Extreme Ultra-Violet (EUV) lithography, the cutting-edge process for semiconductor manufacturing. Through joint development with partners, such as imec, DNP will continue to develop more advanced photomasks capable of supporting processes finer than 3nm and even beyond 2nm.
🇬🇧 A flexible alternative: the UK manufacturer at the forefront of a technology shift in semiconductors
One trend that is common to all parts of the sector however, and driven by the fact that the industry has been built around a very concentrated supply, is the move towards localisation. Economies of scale in conventional semiconductor manufacturing mean that the most efficient method of production is in very large fabs. That leads to very high geographic concentration of supply, and due primarily to historic government incentives, most of that manufacturing takes place in the Far East, particularly in Taiwan and China. Therefore, a key driver for many governments around the world is how to redress the balance and have a supply chain that has less geopolitical exposure.
Because of the disruptive nature of the sector, the UK’s National Semiconductor Strategy was established to focus on areas where the country has distinct competitive strengths which can be sustained over time; namely the type of technology developed by Pragmatic. “Within that, there is an understanding that there needs to be support for semiconductor manufacturing,” he added. An example of this is the Semiconductor Advisory Panel, of which Scott is a member. Established by the Department for Science, Innovation and Technology (DSIT), the panel’s aim is to enable the government to work closely with industry to grow the UK sector, ensuring a stable supply of chips and protecting the UK from national security risks associated with semiconductor technology.
Rapidus and Tenstorrent Partner to Accelerate Development of AI Edge Device Domain Based on 2nm Logic
Rapidus Corporation, a company involved in the research, development, design, manufacture, and sales of advanced logic semiconductors, today announced an agreement with Tenstorrent Inc., a next-generation computing company building computers for AI, to jointly develop semiconductor IP (design assets) in the field of AI edge devices based on 2nm logic semiconductors.
In addition to its AI processors and servers, Tenstorrent built and owns the world’s most performant RISC-V CPU IP and licenses that technology to its customers around the world. Through this technological partnership with Rapidus, Tenstorrent will accelerate the development of cutting-edge devices to meet the needs of the ever-evolving digital society.
Rapidus, University of Tokyo plan 1-nm chip tech with French partner
Japanese chipmaker Rapidus and the University of Tokyo are partnering with French research institute Leti to jointly develop basic technology for designing chips using technology in the 1-nanometer range, Nikkei has learned. The partners will begin actively exchanging staff and sharing technology as early as next year. Leti will contribute its expertise in chip components to build an infrastructure for supplying 1-nm products.
Center For Deep Learning In Electronics Manufacturing: Bringing Deep Learning To Production For Photomask Manufacturing
Five years later, CDLe has completed its mission by graduating more than 20 students from the alliance members and completing 30 DL projects, many of which are headed to or already in production. This contrasts with the opinion of industry luminaries in the 2023 annual eBeam Initiative survey in which only 22% of respondents thought that DL would be used in production in any stage of production mask making by 2023. CDLe and its participants have had more success with DL than the industry at large because of their approach: using digital twins to bridge the data gap that keeps DL prototypes from moving to production use and following a “recipe for DL success” that includes executive commitment, dedicated computing resources, and DL and domain experts.
China develops AI chip 3,000 times faster than Nvidia’s A100
In a major breakthrough for the field of artificial intelligence (AI), scientists from China have recently introduced an extraordinary innovation – the All-Analogue Chip Combining Electronics and Light (ACCEL). During a lab experiment, the ACCEL chip demonstrated an impressive computing speed of 4.6 PFLOPS (peta-floating point operations per second), surpassing the speed of one of the most commonly used commercial AI chips, Nvidia’s A100, by a factor of 3,000. Additionally, researchers noted that the Chinese chip’s energy consumption is a staggering 4 million times lower.
Unlike advanced AI chips such as Nvidia’s A100, which rely on sophisticated lithography machines that China lacks access to, the ACCEL chip was manufactured using a cost-effective 20-year-old transistor fabrication process(180 nm), thanks to China’s Semiconductor Manufacturing International Corporation (SMIC).
Silicon Volley: Designers Tap Generative AI for a Chip Assist
The work demonstrates how companies in highly specialized fields can train large language models (LLMs) on their internal data to build assistants that increase productivity.
The paper details how NVIDIA engineers created for their internal use a custom LLM, called ChipNeMo, trained on the company’s internal data to generate and optimize software and assist human designers. Long term, engineers hope to apply generative AI to each stage of chip design, potentially reaping significant gains in overall productivity, said Ren, whose career spans more than 20 years in EDA. After surveying NVIDIA engineers for possible use cases, the research team chose three to start: a chatbot, a code generator and an analysis tool.
On chip-design tasks, custom ChipNeMo models with as few as 13 billion parameters match or exceed performance of even much larger general-purpose LLMs like LLaMA2 with 70 billion parameters. In some use cases, ChipNeMo models were dramatically better.
Nanoimprint lithography semiconductor manufacturing system that covers diverse applications with simple patterning mechanism
On October 13, 2023, Canon announced today the launch of the FPA-1200NZ2C nanoimprint semiconductor manufacturing equipment, which executes circuit pattern transfer, the most important semiconductor manufacturing process. By bringing to market semiconductor manufacturing equipment with nanoimprint lithography (NIL) technology, in addition to existing photolithography systems, Canon is expanding its lineup of semiconductor manufacturing equipment to meet the needs of a wide range of users by covering from the most advanced semiconductor devices to the existing devices.
Canon’s NIL technology enables patterning with a minimum linewidth of 14 nm2, equivalent to the 5-nm-node3 required to produce most advanced logic semiconductors which are currently available. Furthermore, with further improvement of mask technology, NIL is expected to enable circuit patterning with a minimum linewidth of 10 nm, which corresponds to 2-nm-node.
A NY startup aims to build hundreds of chip factories with prefab parts and AI
To meet the world’s growing hunger for chips, a startup wants to upend the costly semiconductor fabrication plant with a nimbler, cheaper idea, one they believe can faster spread the manufacturing of the chips inside nearly everything we use: an AI-enabled chip factory that can be assembled and expanded modularly with prefab pieces, like high-tech Lego bricks.” “We’re democratizing the ownership of semiconductor fabs,” says Matthew Putman, referring to chip fabrication plants. Putman is the founder and CEO of Nanotronics, a New York City-based industrial AI company that deploys advanced optical solutions for detecting defects in manufacturing procedures.
Its new system, called Cubefabs, combines its modular inspection tools and other equipment with AI, allowing the proposed chip factories to monitor themselves and adapt accordingly—part of what Putman calls an “autonomous factory.” The bulk of the facility can be preassembled, flat-packed and put in shipping containers so that the facilities can be built “in 80% of the world,” says Putman.
Challenges In Ramping New Manufacturing Processes
Teradyne’s Tactics to Tackle Twenty-First Century Test
My interest in Archimedes was spurred by a chat with Eli Roth, who is Product Manager for Smart Manufacturing at Teradyne. Eli was bringing me up to date with the recent launch of Teradyne’s Archimedes Analytics Solution. The Archimedes Analytics Solution employs a Zero-Trust (ZT) model in which data is encrypted throughout. For example, you don’t want anybody to take data off the tester and manipulate it before shipping it out. Thus, Teradyne ensures that all the data coming off the tester is genuine and is essentially “stamped” as being “Teradyne known good”; that is, this is genuine data that came directly off the tester and cannot be manipulated by nefarious scoundrels—it’s data customers can count on.
Two main usage scenarios are depicted below. In the first scenario, data from a Teradyne tester is streamed directly to Teradyne’s edge device in the form of the UltraEdge2000. Featuring the lowest latency, highest performance parallel compute process Teradyne offers, the UltraEdge2000 lives directly in the test cell, thereby providing real-time analytics and real-time actionable data that can be used to make real-time decisions. In addition to Teradyne’s out-of-the-box analytical solutions, customers can employ their own homegrown solutions or solutions from other analytics providers.
Transforming Semiconductor Yield Management with AWS and Deloitte
Together, AWS and Deloitte have developed a reference architecture to enable the aforementioned yield management capabilities. The architecture, shown in Figure 1, depicts how to collect, store, analyze and act on the yield related data throughout the supply chain. The following describes how the modernized yield management architecture enables the six capabilities discussed earlier.
High-NA EUV Progress And Problems
How immersion lithography saved Moore’s Law
In December 2001, ASML researcher Jan Mulkens (now an ASML Fellow) attended an industry conference on 157-nanometer lithography in the United States where industry professionals came together to identify potential next steps. Their discussion honed in on adding a layer of purified water under the lens to sharpen the resolution, an optical phenomenon first discovered and harnessed by microscope pioneers Robert Hooke and Antoni van Leeuwenhoek, and first described for use in lithography by IBM in the 1980s. Jan and his colleagues realized that this optical technique could extend 193-nanometer lithography further, bypassing the industry’s burning challenge of trying to fix 157-nanometer lithography. Furthermore, by using water as the optical fluid, all of the existing optics, masks and photoresists could continue to be used. This was the best chance to keep Moore’s Law going.
“Projecting light through highly purified water would allow significantly smaller chip features to be printed, because the liquid allows the design of an optical lens that more accurately images the fine patterns on the wafer,” explains Jan. “But when we first started thinking about using this principle in a lithography machine, people found it odd. Water was associated with splashes, droplets and bubbles – would that really work in a complex and highly accurate imaging system?” Introducing water into the system that might not flow safely and securely through a hose appeared to be an impossible task.
Automatic Defect Classification in Wafer Fabrication
Semiconductor and MEMS manufacturers around the world are maximizing their yield and reducing expenses through the use of LandingLens. These manufacturers empower advanced technologies and elevate everyday experiences. By implementing automatic defect classification solutions, one of leading manufacturer has achieved a remarkable labor cost reduction of at least 80% wherever these solutions are utilized.
The model training process is not only fast but also produces high-performing models. In addition, LandingLens’ cloud inference service seamlessly integrates into their internal systems. Once a model is deployed, images are automatically queued from their on-premise database and sent to the cloud where a prediction is made and written back to the database. These predictions are used for process control or for making decisions on whether to scrap or not. As a result, a large number of wafer images can now be classified in minutes with increased precision compared to hours.
Using ML For Improved Fab Scheduling
The exact number of available tools for each step varies as tools are taken offline for maintenance or repairs. Some steps, like diffusion furnaces, consolidate multiple lots into large batches. Some sequences, like photoresist processing, must adhere to stringent time constraints. Lithography cells must match wafers with the appropriate reticles. Lot priorities change continuously. Even the time needed for an individual process step may change, as run-to-run control systems adjust recipe times for optimal results.
At the fab level, machine learning can support improved cycle time prediction and capacity planning. At the process cell or cluster tool level, it can inform WIP scheduling decisions. In between, it can facilitate better load balancing and order dispatching. As a first step, though, all of these applications need accurate models of the fab environment, which is a difficult problem.
The GlobalFoundries group demonstrated the effectiveness of neural network methods for time constraint tunnel dispatching. The relationship between input parameters and cycle time is complex and non-linear. As discussed above, machine learning methods are especially useful in situations like this, where statistical data is available but exact modeling is difficult.
Predictive Maintenance for Semiconductor Manufacturers with SEEQ powered by AWS
There are challenges in creating predictive maintenance models, such as siloed data, the offline nature of data processing and analytics, and having the necessary domain knowledge to build, implement, and scale models. In this blog, we will explore how using Seeq software on Amazon Web Services can help overcome these challenges.
The combination of AWS and Seeq pairs a secure cloud services platform with advanced analytics innovation. Seeq on AWS can access time series and relational data stored in AWS data services including Amazon Redshift, Amazon DynamoDB, Amazon Simple Storage Service (S3), and Amazon Athena. Once connected, engineers and other technical staff have direct access to all the data in those databases in a live streaming environment, enabling exploration and data analytics without needing to go through the steps to extract data and align timestamps whenever more data is required. As a result, monitoring dashboards and running reports can be set to auto generate and are easily shared among groups or sites. This enables balancing machine downtimes and planning ahead for maintenance without disrupting schedules or compromising yields.
How SCARA, Six-Axis, and Cartesian Pick-And-Place Robotics Optimize and Streamline Electronics Manufacturing Processes
Hastening the adoption of robotics in semiconductor manufacture are burgeoning classes of six-axis robots, selective compliance assembly robot arms (SCARAs), cartesian machinery, and collaborative robots featuring reconfigurable or modular hardware as well as unifying software to greatly simplify implementation. These robots and their supplemental equipment must be designed, rated, and installed for cleanroom settings or else risk contaminating delicate wafers with impurities. Requirements are defined by ISO 14644-1:2015, which classifies cleanroom air cleanliness by particle concentration.
Advanced cleanroom-rated robotic end-of-arm tooling (EoAT or end effectors) such as grippers are core to semiconductor production. Here, EOATs must have high dynamics and the ability to execute tracing, placing, and assembling with exacting precision. In some cases, EoAT force feedback or machine vision boosts parts-handling accuracy by imparting adaptive capabilities — so pick-and-place routines are quickly executed even if there’s some variability in workpiece positions, for example. Such sensor and feedback advancements can sometimes render the complicated electronics-handling fixtures of legacy solutions unnecessary.
Athinia™ expands partnerships to include Tokyo Electron for real-time collaborative analytics of semiconductor fab equipment performance
Athinia™ announced that its industry-wide many-to-many data ecosystem to accelerate digital transformation and further enable cutting-edge AI is being adopted by more organizations globally. Tokyo Electron Limited (TEL;TYO:8035), a leading capital equipment manufacturer of cutting-edge semiconductor production equipment and technical service will use Athinia™ as a key solution to accelerate its digital and cloud transformation.
By granting access to limitless analytics capabilities, including sophisticated AI and machine learning frameworks, the Athinia™ platform enables the participants in the semiconductor industry to differentiate based on quality, performance, and time to market. Feedback is provided in real time. Powered by Palantir, the platform allows users to structure and analyze data from disparate sources, generate powerful insights, and support operational decisions, all while helping to ensure that sensitive data is processed in accordance with applicable data privacy rules, regulations, and norms.
⛓️ ASML says decoupling chip supply chain is practically impossible
“We do not believe in ASML that decoupling is possible. We believe this will be extremely difficult and extremely expensive,” Fouquet told Nikkei at the company’s headquarters. “It’s a matter of time until people realize that the only way to be successful in semiconductors is through cooperation.” The secret to ASML’s success, according to Fouquet, is its longtime collaboration with critical global suppliers such as Zeiss and Cymer and the support from its top chipmaking customers, Taiwan Semiconductor Manufacturing Co. and Intel.
The bulk of ASML’s production, meanwhile, is done in one place, its headquarters, and Fouquet said it will likely keep the majority – about 80% to 90% – of its production and integration there until at least 2026. “It’s very important for us to keep R&D and manufacturing together,” the senior executive said.
Samsung to apply AI, big data tech to entire chipmaking process
In partnership with the Samsung Advanced Institute of Technology (SAIT), Samsung’s Device Solutions (DS) division, which oversees its semiconductor business, will lead the company’s efforts to broaden the use of AI throughout the chipmaking process, sources familiar with the matter said on Monday. Under the plan, Samsung will seek to apply AI tech to DRAM design automation, chip material development, foundry yield improvement, mass production and chip packaging.
Specifically, the company hopes its AI tech will determine the cause of unnecessary wafer losses, optimize the AI-based manufacturing process and analyze DRAM product defects, sources said.
Tokyo Electron Develops Memory Channel Hole Etch Technology That Enables Ultra-fast 10-µm-deep Etching for 3D NAND Flash with Over 400 Layers and an 84% Reduction of Global Warming Potential
Tokyo Electron announced that its development team at Tokyo Electron Miyagi—the development and manufacturing site for its plasma etch systems—has developed an innovative etch technology capable of producing memory channel holes in advanced 3D NAND devices with a stack of over 400 layers. The new process developed by the team has brought dielectric etch application to the cryogenic temperature range for the first time, producing a system with exceptionally high etch rates. The innovative technology not only enables a 10-µm-deep etch with a high aspect ratio* in just 33 minutes, but also can reduce the global warming potential by 84% compared with previous technologies. The geometry of the etched structure is quite well-defined as shown in the figure 1. Potential innovations enabled by this technology will spur creation of 3D NAND flash memory with even larger capacity.
Why vibration control is key to semiconductor manufacturing
Although these manufacturing sites can be vast, most of the equipment is not directly used in the manufacture of silicon chips. Manufacturing at the nanoscale requires highly controlled conditions, so the fabs require an extensive range of heating, cooling and filtration systems. This plant equipment makes up approximately 90% of the equipment located at a typical fab.
This equipment ensures the correct temperature, humidity level and particulate level for the optimal production of chips. However, while solving one problem, it also introduces another. Mechanical systems and HVAC systems all generate vibration which, if left unmitigated, could disrupt sensitive precision manufacturing processes and interfere with chip production. ‘‘Vibration control is key to making these things work,’’ Adam explained.
One of the unique features of this project was the vast scale. In total, there were approximately 130 kilometres of piping and 3.2 kilometres of ductwork. The project therefore required a staggering 3,800 mounts. ‘‘I’ve worked on all sorts of projects at this stage of my career, but nothing can touch this one in terms of scale. Nothing is even close,’’ Adam reflected.
The Impact Of Machine Learning On Chip Design
AutoDMP Finds Efficient Ways To Place Transistors On Silicon Chips
Macro placement is a critical very large-scale integration (VLSI) physical design problem that significantly impacts the design powerperformance-area (PPA) metrics. This paper proposes AutoDMP, a methodology that leverages DREAMPlace, a GPU-accelerated placer, to place macros and standard cells concurrently in conjunction with automated parameter tuning using a multi-objective hyperparameter optimization technique. As a result, we can generate high-quality predictable solutions, improving the macro placement quality of academic benchmarks compared to baseline results generated from academic and commercial tools. AutoDMP is also computationally efficient, optimizing a design with 2.7 million cells and 320 macros in 3 hours on a single NVIDIA DGX Station A100. This work demonstrates the promise and potential of combining GPU-accelerated algorithms and ML techniques for VLSI design automation
Pattern-Shaping System Speeds Up Chip Production
Applied Materials has introduced its new Centura Sculpta pattern-shaping system that promises to provide a cost-effective alternative to extreme ultraviolet (EUV) lithography double patterning used to print dense interconnect lines and vias. As a result, the solution can reduce the number of EUV steps, production complexity and costs while potentially improving yields.
To keep advancing transistor performance, power consumption and density, chipmakers must adopt more sophisticated process technologies with tighter critical dimensions. Usage of dual EUV exposure is inevitable to print smaller features with 3-nm, 2-nm and thinner nodes. But double EUV patterning is expensive, lengthy and resource-consuming.
IBM and Rapidus Form Strategic Partnership to Build Advanced Semiconductor Technology and Ecosystem in Japan
IBM (NYSE: IBM) and Rapidus today announced a joint development partnership to advance logic scaling technology as part of Japan’s initiatives to become a global leader in semiconductor research, development, and manufacturing.
Rapidus Corporation researches, develops, designs, manufactures, and sells advanced logic semiconductors, and was established with the endorsement of major Japanese companies. As part of this agreement, Rapidus and IBM will further develop IBM’s breakthrough 2 nanometer (nm) node technology for implementation by Rapidus at its fab in Japan.
Imec and Rapidus sign Memorandum of Cooperation to collaborate on advanced semiconductor technologies
Rapidus plans to mass-produce chips with state-of-the-art 2-nanometer technology in Japan in the latter half of this decade. Such advanced chips can be used for 5G communications, quantum computing, data centers, self-driving vehicles, and digital smart cities. Imec intends to support Rapidus in the research and development of leading-edge technology. For this, Rapidus and imec express their intention to set up a strategic partnership, with Rapidus becoming a core partner in imec’s leading advanced nanoelectronics program. The MOC also contemplates collaboration with the nearly established Leading-edge Semiconductor Technology Center (LSTC), which will serve as a research and development hub for beyond 2-nanometer technologies in Japan. With the MOC, all parties subscribe to the importance of worldwide collaboration and regional strengthening of semiconductor ecosystems, in particular the ecosystem in Japan.
How Chip Giant AMD Finally Caught Intel
Designing in the Age of AI
Development of New Technology for Wastewater Treatment for Semiconductor Production
Alcohols are used to remove impurities on the surface of semiconductors or electronics during the manufacturing process, and wastewater containing alcohols is treated using reverse osmosis, ozone, and biological decomposition. Although such methods can lower the alcohol concentration in wastewater, they are ineffective at completely decomposing alcohols in wastewater with a low alcohol concentration. This is because alcohol is miscible in water, making it impossible to completely separate from alcohol using physical methods, while chemical or biological treatments are highly inefficient. For this reason, wastewater with a low alcohol concentration is primarily treated by diluting it with a large amount of clean water before its discharge.
The research team employed Fenton oxidation that uses oxidizing agents and catalysts during the advanced oxidation process for water treatment. Usually alcohols were used as reagents to verify radical production during Fenton oxidation in other advanced oxidation process (AOP) studies, they were the target for removal from semiconductor wastewater in this research. This water treatment technology is expected to dramatically reduce the cost and water resources invested into the treatment of semiconductor wastewater. In the past, clean water with a volume 10 times higher than that of the wastewater under treatment was required for dilution of the wastewater in order to reduce the alcohol concentration of 10 ppm in the wastewater to less than 1 ppm.
Could Reinforcement Learning play a part in the future of wafer fab scheduling?
However, as the use of RL for JSS problems is still a novelty, it is not yet at the level of sophistication that the semiconductor industry would require. So far, the approaches can handle standard small problem scenarios but cannot handle flexible problems or batching decisions. Many constraints need to be obeyed in wafer fabs (e.g., timelinks and reticle availability) and it is not easily guaranteed that the agent will adhere to them. The objective set for the agent must be defined ahead of training, which means that any change made afterwards will require a repeat of training before new decisions can be obtained. This is less problematic for solving the instance proposed by Tassel et al., although their approach relies on a specifically modelled reward function which would not easily adapt to changing objectives.
Making The Most Of Data Lakes
Data management and data analysis necessitates understanding the data storage and data compute options to design an optimal solution. This is made more difficult by the sheer volume of data generated by the design and manufacturing of semiconductor devices. There are more sensors being added into equipment, more complex heterogeneous chip architectures, and increased demands for reliability — which in turn increase the amount of simulation, inspection, metrology, and test data being generated.
Connecting different data sources is extremely valuable. It allows feed-forward decisions on manufacturing processes (package type, skipping burn-in), and feedback in order to trace causes of excursions (yield, quality, and customer returns).
“An understanding of the semiconductor manufacturing process and relationships throughout are essential for some applications,” said Jeff David, vice president of AI solutions at PDF Solutions. “For example, how can I use wafer equipment history and tool sensor data to predict the failure propensity of a chip at final test? How does time delay between process and test steps determine what data is useful in finding a root cause of a failure mode? What failure modes are predictable with which datasets? How do preceding process steps affect the data collected at a given process step?”
Improving Yield With Machine Learning
Machine learning is becoming increasingly valuable in semiconductor manufacturing, where it is being used to improve yield and throughput.
Synopsys engineers recently found that a decision tree deep learning method can classify 98% of defects and features at 60X faster retraining time than traditional CNNs. The decision tree utilizes 8 CNNs and ResNet to automatically classify 12 defect types with images from SEM and optical tools.
Macronix engineers showed how machine learning can expedite new etch process development in 3D NAND devices. Two parameters are particularly important in optimizing the deep trench slit etch — bottom CD and depth of polysilicon etch recess, also known as the etch stop.
KLA engineers, led by Cheng Hung Wu, optimized the use of a high landing energy e-beam inspection tool to capture defects buried as deep as 6µm in a 96-layer ONON stacked structure following deep trench etch. The e-beam tool can detect defects that optical inspectors cannot, but only if operated with high landing energy to penetrate deep structures. With this process, KLA was looking to develop an automated detection and classification system for deep trench defects.
Finding Frameworks For End-To-End Analytics
New standards, guidelines, and consortium efforts are being developed to remove these barriers to data sharing for analytics purposes. But the amount of work required to make this happen is significant, and it will take time to establish the necessary level of trust across groups that historically have had minimal or no interactions.
For decades, test program engineers have relied upon the STDF file format, which is inadequate for today’s use cases. STDF files cannot dynamically capture adaptive test limits, and they are unable to assist in real-time decisions at the ATE based upon current data and analytically derived models. In fact, most data analytic companies run a software agent on the ATE to extract data for decisions and model building. With ATE software updates, the agent often breaks, requiring the ATE vendor to fix each custom agent on every test platform. Emerging standards, TEMS and RITdb, address these limitations and enable new use cases.
But with a huge amount of data available in manufacturing settings, an API may be the best approach for sharing sensitive data from point of origin to a centralized repository, whether on-premise or in the cloud.
Designing Billions of Circuits with Code
Bringing EDA to silicon helped solve daunting challenges in chip making. A chip is built in layers. Now you have to wire connections in 3-D, taking into consideration layer-to-layer connections called vias.
Origin of the FOUP
The Race To Zero Defects In Auto ICs
While semiconductor test engineers are making great strides on isolating fab-generated defects, assembly engineers are quietly focusing attention on improving inspection and processing of equipment data to catch latent defects. This is a big deal for automotive electronics. According to a BMW presentation at the 2017 Automotive Electronics Council reliability workshop, most semiconductor devices fail within the car’s warranty period.
The carmaker noted that 22% of warranty costs are due to electronics and electrical control units. Of those failed parts, BMW said 77% of the failures are semiconductor devices, and 23% of the parts are isolated to active and passive components. Of those semiconductor failures, 48% were due to systematic fails, 24% to test coverage, 15% to random failures, and 6% were retested and did not fail the second time. The failure pareto was also broken down to 41% final test, 24% front-end processing, 22% design, and 12% assembly.
For assembly facilities to deliver 10 dppb quality to their automotive customers, they need to learn from customer returns. This requires investment in assembly equipment data collection and traceability. Latent defects that become activated during the warranty period yet pass electrical test necessitates 100% inspection to screen for these failures. Yet all this investment in more inspection and data collection places a financial strain on traditionally inexpensive assembly operations. There is constructive tension between assembly facilities and their automotive customers, as they are both cost-sensitive. Still, somehow this pathway to 10 dppb will be funded.
AI-Powered Verification
“We see AI as a disruptive technology that will in the long run eliminate, and in the near term reduce the need for verification,” says Anupam Bakshi, CEO and founder of Agnisys. “We have had some early successes in using machine learning to read user specifications in natural language and directly convert them into SystemVerilog Assertions (SVA), UVM testbench code, and C/C++ embedded code for test and verification.”
There is nothing worse than spending time and resources to not get the desired result, or for it to take longer than necessary. “In formal, we have multiple engines, different algorithms that are working on solving any given property at any given time,” says Pete Hardee, director for product management at Cadence. “In effect, there is an engine race going on. We track that race and see for each property which engine is working. We use reinforcement learning to set the engine parameters in terms of which engines I’m going to use and how long to run those to get better convergence on the properties that didn’t converge the first time I ran it.”
Deep Learning For Industrial Inspection
Where And When End-To-End Analytics Works
To control a wafer factory operation, engineering teams rely on process equipment and inspection statistical process control (SPC) charts, each representing a single parameter (i.e., univariant-based). With the complexities of some processes the interactions between multiple parameters (i.e., multi-variant) can result in yield excursions. This is when engineers leverage data to make decisions on subsequent fab or metrology steps to improve yield and quality.
“When we look at fab data today, we’re doing that same type of adaptive learning,” McIntyre said. “If I start seeing things that don’t fit my expected behavior, they could still be okay by univariate control, but they don’t fit my model in a multi-variate sense. I’ll work toward understanding that new combination. For instance, in a specific equipment my pump down pressure is high, but my gas flow is low and my chamber is cold, relatively speaking, and all (parameters) individually are in spec. But I’ve never seen that condition before, so I need to determine if this new set of process conditions has an impact. I send that material to my metrology station. Now, if that inline metrology data is smack in the center, I can probably disregard the signal.”
The X-Ray Tech That Reveals Chip Designs
When you’re baking a cake, it’s hard to know when the inside is in the state you want it to be. The same is true—with much higher stakes—for microelectronic chips: How can engineers confirm that what’s inside has truly met the intent of the designers? The new version of our X-ray technique, called ptychographic X-ray laminography, can uncover the interconnect structure of entire chips without damaging them, even down to the smallest structures. Using that technique, we could easily discover a (deliberate) discrepancy between the design file and what was manufactured.
Although we can already tell a lot about an IC from just the layout of its interconnects, with further improvements we should be able to discover everything about it, including the materials it’s made of. For the 16-nm-technology node, that includes copper, aluminum, tungsten, and compounds called silicides. We might even be able to make local measurements of strain in the silicon lattice, which arises from the multilayer manufacturing processes needed to make cutting-edge devices.
Why The World Relies On ASML For Machines That Print Chips
Metrology Primer
The cost of defect failures is starting to spiral out of control, and the cheapest insurance against this is more Metrology and Inspection. One of the changes the industry is adopting is advanced packaging as the primary driver to increasing semiconductor performance. The push to advanced packaging has an entire set of consequences, namely newer packaging technology and a new vector of failure.
Additionally, Metrology and Inspection spending tends to ramp before the rest of the tools, and that is why they should continue to grow so robustly in 2022 given that large fabs are just starting to come online. Metrology and inspection ramps are likely happening currently for the N3 and N5 nodes at TSMC and Intel.
Semiconductor growth through as-a-service models
This report examines As-a-Service (AaS) as an increasingly relevant competitive growth model for the semiconductor industry. Originally successful in the software realm, AaS business models are poised to help semiconductor companies fuel growth, boost revenue, innovate faster, and deepen relationships with customers. When planned and implemented correctly, AaS can substantially increase shareholder value and improve predictability of revenue. However, if executed poorly, it can negatively impact a company’s bottom line.
Improving PPA In Complex Designs With AI
The goal of chip design always has been to optimize power, performance, and area (PPA), but results can vary greatly even with the best tools and highly experienced engineering teams. AI works best in design when the problem is clearly defined in a way that AI can understand. So an IC designer must first see if there is a problem that can be tied to a system’s ability to adapt to, learn, and generalize knowledge/rules, and then apply these knowledge/rules to an unfamiliar scenario.
PHOTOS: There Aren't Enough Chips — Why Are They So Hard to Make?
From the lab to high above the factory floor, wafers move through a complex process before they are completed. The Wall Street Journal has an interactive slide show documenting the process.
The Extreme Engineering of ASML’s EUV Light Source
Big Payback For Combining Different Types Of Fab Data
Collecting and combining diverse data types from different manufacturing processes can play a significant role in improving semiconductor yield, quality, and reliability, but making that happen requires integrating deep domain expertise from various different process steps and sifting through huge volumes of data scattered across a global supply chain.
How Japan Won Lithography (& Why America Lost)
Chip floorplanning with deep reinforcement learning
Inside Intel’s Bold $26 Billion U.S. Plan To Regain Chip Dominance
What’s Harder to Find Than Microchips? The Equipment That Makes Them
We typically associate microchips with the latest and greatest technology, but it turns out that most of the chips that go into the products we use are made with older manufacturing techniques. No one knows precisely what proportion of the world’s microchips is made on used equipment, but Mr. Howe, owner of SDI Fabsurplus, estimates it might be as much as a third.
TSMC is expanding its capacity to make older chips by building a new plant for that purpose in Japan. Intel has no plans to build new capacity for manufacturing older kinds of chips, and continues to concentrate on making bleeding-edge chips, says Lisa Spelman, a vice president in Intel’s data-center group.
The Semiconductor Health and Cancer Problem
How ASML Won Lithography (& Why Japan Lost)
Inside TSMC, the Taiwanese chipmaking giant building a new plant in Phoenix
Taiwan Semiconductor Manufacturing Company may not be a household name, but with a market value of over $550 billion, it’s one of the world’s 10 most valuable companies. Now, it’s leveraging its considerable resources to bring the world’s most advanced chip manufacturing back to U.S. soil.
CNBC got an exclusive tour of the $12 billion fabrication plant, or fab, in Phoenix, Arizona, where TSMC will start making 5-nanometer chips in 2024. The company says it will produce 20,000 wafers each month.
Economics of the FPGA
Successive generations of chips are becoming harder to justify where smaller process geometries become nonlinearly more expensive. An increased integration however, drives up packaging complexity and cost. This increase in complexity grows design time and expense. Because of these factors, the margins with which to gain profit from the volume production of ICs are reducing. First, the increase in competition allows for more consumer choices, which reduces per-product volumes. This increase in competition also reduces the life duration and lifetime volume of products. New compute-intensive nodes and technologies must be increasingly agile, not only to support the changing market demands but also to keep up with upgrading deep-learning models. There is an apparent lack of FPGAs being used for AI applications that sit in the “middle of the road” in terms of complexity, causing designers to rely either on custom chiplets or embedded processors for hardware acceleration. The new FPGA economy paradigm opened by Efinix frees designers to more flexibly innovate in a realm that will deliver revolutionary benefits to society. This once-in-a-lifetime quantum shift in product design possibilities is providing an inflection point away from the dead end of custom silicon and into the customizable blank slate of FPGA fabric.
Moore’s Law Could Ride EUV for 10 More Years
ASML expects that chip makers ramping up production with the new technology initially will use 0.55 NA for a cost-saving single-expose EUV process for advanced wafer layers, while using multi-pattern 0.33 NA along with older lithography technology for more mature nodes. As the single-expose 0.55 NA technology reaches its limits, somewhere around six years from now, ASML predicts that chipmakers will once again resort to multi-patterning to reach even more advanced nodes with higher transistor densities. In the next few years, ASML’s introduction of 0.55 NA tools will help leading semiconductor foundries like TSMC overcome obstacles they are now encountering at the 3nm chip process technology node.
The Dutch company is the world’s lone supplier of EUV equipment. In 2010, ASML shipped the first prototype EUV tool to an undisclosed Asian customer. Semiconductor production today is divided into the EUV “haves” like Taiwan Semiconductor Manufacturing Co. (TSMC), Samsung and Intel, which make advanced chips for customers like Apple, MediaTek and Qualcomm. The EUV “have not” chip makers years ago threw in the towel at leading nodes, jettisoning the associated multi-billion dollar capital expenditures and focusing on improved profits from legacy production lines and products that benefit little or none from process shrinks.
Europe’s new €1.6bn chip plant needs only 10 workers on factory floor
A 60,000 square meter facility built specializing in power semiconductors seeks ease bottlenecks for major automotive clients. The increase in automation solutions has made localized European production of semiconductors possible. By reducing comparable personnel needed to run the facility from 150 to 10 makes the factory cost competitive with factories in Asia.
Fabs Drive Deeper Into Machine Learning
For the past couple decades, semiconductor manufacturers have relied on computer vision, which is one of the earliest applications of machine learning in semiconductor manufacturing. Referred to as Automated Optical Inspection (AOI), these systems use signal processing algorithms to identify macro and micro physical deformations.
Defect detection provides a feedback loop for fab processing steps. Wafer test results produce bin maps (good or bad die), which also can be analyzed as images. Their data granularity is significantly larger than the pixelated data from an optical inspection tool. Yet test results from wafer maps can match the splatters generated during lithography and scratches produced from handling that AOI systems can miss. Thus, wafer test maps give useful feedback to the fab.
The Big Semiconductor Water Problem
The $150 Million Machine Keeping Moore’s Law Alive
ASML’s next-generation extreme ultraviolet lithography machines achieve previously unattainable levels of precision, which means chips can keep shrinking for years to come.
ASML introduced the first extreme ultraviolet (EUV) lithography machines for mass production in 2017, after decades spent mastering the technique. The machines perform a crucial role in the chipmaking ecosystem, and they have been used in the manufacture of the latest, most advanced chips, including those in new iPhones as well as computers used for artificial intelligence. The company’s next EUV system, a part of which is being built in Wilton, Connecticut, will use a new trick to minimize the wavelength of light it uses—shrinking the size of features on the resulting chips and boosting their performance—more than ever before.
TWINSCAN: 20 years of lithography innovation
“It was limited new technology, but what was a revolution about the TWINSCAN was the swapping of the stages,” says Bert. “Lots of things were normal developments, but that chuck swap was different. We just had to make it work.”
And thus, the TWINSCAN platform was born. TWINSCAN was the first – and is still the only – lithography system platform with two complete wafer table modules (or wafer stages). Wafers are loaded onto the wafer table modules alternately. When the wafer on table one is being exposed, another wafer is loaded on table two and then aligned and mapped. The tables then swap position so that the wafer on table two is exposed while the wafer on table one is unloaded. A new wafer is then loaded, aligned and mapped.
Semiconductor Manufacturing: Making Impossibly Small Features
Deposition, litho, and etch are interdependent processes tightly linked together. Technology continues to press forward to meet the incredible opportunity of 5G, cloud, and IoT, and these processes enable our customers to go further by reducing feature sizes and improving pattern fidelity to get a better feature. The litho process can produce lines that have some edge roughness, which can have a negative impact on the variability of the devices you make because it affects what are called “critical dimensions,” such as the transistor gate length. We can also take litho printed lines and improve the sidewall smoothness by typically 30% or more.
Motion Control, Mechatronics Design, and Moore's Law
Technology in a broad sense is driven by developments in semiconductor technology, particularly with respect to the computational power of devices and systems, as well as sensor technology. The progress of semiconductor technology has demonstrated an exponential curve since the middle of the previous century, representing Moore’s Law. Consequently, it is of utmost importance to bridge the gaps between disciplines in the fields of control, automation, and robotics. Moreover, data-driven approaches need to be combined with model-based design. This will lead to new digital twinning and automated design approaches that provide major opportunities. Furthermore, this necessitates the redefinition of our university system.
Aiming for the Top in Industrial AI, SK’s First AI Company Gauss Labs
Gauss Labs has been developing AI solutions aimed at maximizing production efficiency using the massive amount of data generated at SK hynix’s production sites. SK hynix wishes to make the overall semiconductor production process more intelligent and optimized across all procedures including process management, yield prediction, equipment repair and maintenance, materials measurement, and defect testing and prevention.
Challenges to Interconnect Scaling at 3nm and Beyond
Interconnects consist of two key metal components: the metal lines that transfer current within the same device layer and the metal vias that transfer current between layers. Pitch reduction narrows the width of both and increases resistance along with the time needed to move signals across distances. It also increases the voltage drop across a circuit, throttling circuit speed and increasing power dissipation.
While transistor performance improves with scaling, the same cannot be said for interconnect metals. In fact, as dimensions shrink, interconnect via resistance can increase by a factor of 10 (see Figure 1). This results in resistive-capacitive (RC) delays that reduce performance. It also increases power consumption. Interconnects consume close to one third of device power and account for more than 75 percent of RC delay, so improving interconnect resistance is the best way to improve overall device performance.
To enable logic scaling to continue, the industry is developing a new architecture called buried power rail with backside power delivery network (see Figure 4). This architecture routes power to the transistor cell from the back side of the silicon wafer, beneath the transistors. The approach is expected to provide three important benefits: improving voltage losses by as much as 7X; allowing the transistor cell area to be scaled by 20-33 percent; and leaving more cell space for the signal lines which also incur resistance from scaling.
MacroFab: Driving The Cloud-Based Transformation Of Electronics Manufacturing
The company brings cloud-based, manufacturing-as-a-service (MaaS) solutions to the electronics industry. On its platform, companies can upload component designs, obtain quotes, place orders and follow the progress towards delivery. Companies can price and order a wide range of parts and products, from printed circuit boards (PCB) to fully assembled and packaged electronics products.
IBM Unveils World's First 2 Nanometer Chip Technology, Opening a New Frontier for Semiconductors
IBM (NYSE: IBM) today unveiled a breakthrough in semiconductor design and process with the development of the world’s first chip announced with 2 nanometer (nm) nanosheet technology. Semiconductors play critical roles in everything from computing, to appliances, to communication devices, transportation systems, and critical infrastructure.
The potential benefits of these advanced 2 nm chips could include:
- Quadrupling cell phone battery life, only requiring users to charge their devices every four days.
- Slashing the carbon footprint of data centers, which account for one percent of global energy use. Changing all of their servers to 2 nm-based processors could potentially reduce that number significantly.
- Drastically speeding up a laptop’s functions, ranging from quicker processing in applications, to assisting in language translation more easily, to faster internet access.
- Contributing to faster object detection and reaction time in autonomous vehicles like self-driving cars.
AI In Inspection, Metrology, And Test
“The human eye can see things that no amount of machine learning can,” said Subodh Kulkarni, CEO of CyberOptics. “That’s where some of the sophistication is starting to happen now. Our current systems use a primitive kind of AI technology. Once you look at the image, you can see a problem. And our AI machine doesn’t see that. But then you go to the deep learning kind of algorithms, where you have very serious Ph.D.-level people programming one algorithm for a week, and they can detect all those things. But it takes them a week to program those things, which today is not practical.”
That’s beginning to change. “We’re seeing faster deep-learning algorithms that can be more easily programmed,” Kulkarni said. “But the defects also are getting harder to catch by a machine, so there is still a gap. The biggest bang for the buck is not going to come from improving cameras or projectors or any of the equipment that we use to generate optical images. It’s going to be interpreting optical images.”
Scaling AI in the sector that enables it: Lessons for semiconductor-device makers
Because of their high capital requirements, semiconductor companies operate in a winner-takes-most or winner-takes-all environment. Consequently, they have persistently attempted to shorten product life cycles and aggressively pursue innovation to introduce products more quickly and stay competitive. But the stakes are getting increasingly high. With each new technology node, expenses rise because research and design investments, as well as capital expenditures for production equipment, increase drastically as structures get smaller. For example, research and design costs for the development of a chip increased from about $28 million at the 65 nanometer (nm) node to about $540 million at the leading-edge 5 nm node (Exhibit 1). Meanwhile, fab construction costs for the same nodes increased from $400 million to $5.4 billion.
As companies attempt to increase productivity within research, chip design, and manufacturing while simultaneously accelerating time to market, AI/ML is becoming an increasingly important tool along the whole value chain.
Run Semiconductor Design Workflows on AWS
This implementation guide provides you with information and guidance to run production semiconductor workflows on AWS, from customer specification, to front-end design and verification, back-end fabrication, packaging, and assembly. Additionally, this guide shows you how to build secure chambers to quickly enable third-party collaboration, as well as leverage an analytics pipeline and artificial intelligence/machine learning (AI/ML) services to decrease time-to-market and increase return on investment (ROI). Customers that run semiconductor design workloads on AWS have designed everything from simple ASICs to large SOCs with tens of billions of transistors, at the most advanced process geometries. This guide describes the numerous AWS services involved with these workloads, including compute, storage, networking, and security. Finally, this paper provides guidance on hybrid flows and data transfer methods to enable a seamless hybrid environment between on-premises data centers and AWS.
Edge-Inference Architectures Proliferate
What makes one AI system better than another depends on a lot of different factors, including some that aren’t entirely clear.
The new offerings exhibit a wide range of structure, technology, and optimization goals. All must be gentle on power, but some target wired devices while others target battery-powered devices, giving different power/performance targets. While no single architecture is expected to solve every problem, the industry is in a phase of proliferation, not consolidation. It will be a while before the dust settles on the preferred architectures.
Intel Problems
The misplaced optimism is twofold: first there is the fact that eight years later Intel has again appointed a new CEO (Pat Gelsinger), not to replace the one I was writing about (Brian Krzanich), but rather his successor (Bob Swan). Clearly the opportunity was not seized. What is more concerning is that the question is no longer about seizing an opportunity but about survival, and it is the United States that has the most to lose.
Early And Fine Virtual Binning
ProteanTecs enables manufacturers to bin chips virtually, in a straightforward and inexpensive way based on Deep Data. By using a combination of tiny on-chip test circuits called “Agents” and sophisticated AI software, chip makers can find relationships between any chip’s internal behavior and the parameters measured during the standard characterization process. Those relationships can be used to measure similar chips’ internal characteristics at wafer sort to precisely predict how chips would perform during Final Test, even before the wafer is scribed.
Hyperspectral imaging at imec
Early And Fine Virtual Binning
ProteanTecs, which provides an AI platform to monitor chip reliability, today closed a $45 million funding round. The company says the fresh capital will bolster its go-to-market strategy and operations as it seeks to scale worldwide.
Chip design and manufacturing is a high-risk, high-reward pursuit. Mistakes made during the earliest phases are often enormously costly — chip fabrication plants cost billions to build. And the most sophisticated hardware can take years to hammer out, with intense speculation about how to optimize the next generation for workloads that might come into vogue.